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I had K of cache installed, which can sometimes influence what fastest cache timings are stable. Since I’d likely never need to use the 4V option, I could always replace the relevant divider resistor to change the 4V selection to 3. I could probably epoxy an angled pin header right to the top of the clock sli to add third jumper. Dual Xeon X 4. Then I put sticks fromm and in the machine assuming that they are FPM memory but I’m getting the same results as al.

That is the case with SiS boards anyway.

M1487 B1 M1489 A1 M1451A1 M1431 A2

I’ll have to take a look at modbin, it would certainly be useful to have some control over parity since most of my DRAM modules are bit. This site hosts no abandonware. If anyone in the states has a spare S3 Treo64 they’d like to send I’d gratefully accept, otherwise I can hunt one down on eBay. I’d like to be sure it’s an even comparison One thing to note: This board isn’t as popular as the LS there’s barely any information available. This really limits its usefullness with an Am5x or Cyrix 5x I’d use a trimmer rather than a fixed resistor if you’re testing for an IBM 5x Thanks for the detailed reply!


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I’m also adding the manual in case someone stumbles over this thread in the future and needs it. Ideally, I would like to run a more thorough comparison and update this thread, viewtopic. And stick with K cache. Does anyone familiar with either of these boards have any comments or suggestions on any particular settings I may need to adjust on either board that may account for such a dramatic difference?

If I remember correctly. Others will run well at 3. You do not have the required permissions to view the files attached to this post. Faster than SiS as well. Has anyone else experienced this?

[SAA] Am5X86-P75-S ALi m1489 ALi M1487 T65550 ISA bus Industrial Motherboard

Parity should theoretically decrease performance since it’s more overhead for the chipset to calculate the parity bits, so for the purpose of testing I was hoping to ensure parity isn’t being used on either board. The 3 jumpers to the right of the clock generator controls the FSB. I bought these two boards from a Ukrainian eBay seller and after some minor repairs both are in tip-top shape. The LSe manual I have aali explain what the individual CPU selection jumpers are, only where to put them for a particular processor.


When I get some time tonight I’ll look closer and see if I can figure out which jumpers are for the multipliers.

PC Chipsets documentation: ALi

I’m looking forward to your test results of EDO vs. I didn’t have time to save the results, but I hope to get back to it tomorrow since I’ll have the house to myself for most of the day. If you don’t want to remove the sticker, you can usually tell if it is UV EPROM by noticing the thickness of the chip and the sandwich look to it.

Sure enough the memory benchmarks dropped by a pretty noticeable amount, so it does seem like the ALi chipset will indeed leverage EDO RAM when available and unlike SIS, provides a tangible improvement in performance.

I have never witnessed first hand or second hand any improved benchmark results when using EDO on a PCI motherboard. I checked the ram sticks and 2 of them out of 3 were EDO.

I’d be happy run some time demos. Perhaps RAM write to 1 ws.